Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry

ABSTRACT

Methods of forming contact openings, making electrical interconnections, and related integrated circuitry are described. Integrated circuitry formed through one or more of the inventive methodologies is also described. In one implementation, a conductive runner or line having a contact pad with which electrical communication is desired is formed over a substrate outer surface. A conductive plug is formed laterally proximate the contact pad and together therewith defines an effectively widened contact pad. Conductive material is formed within a contact opening which is received within insulative material over the effectively widened contact pad. In a preferred implementation, a pair of conductive plugs are formed on either side of the contact pad laterally proximate thereof. The conductive plug(s) can extend away from the substrate outer surface a distance which is greater or less than a conductive line height of a conductive line adjacent which the plug is formed. In the former instance and in accordance with one aspect, such plug(s) can include a portion which overlaps with the contact pad of the associated conductive line.

TECHNICAL FIELD

[0001] This invention relates to semiconductor processing methods offorming contact openings, methods of forming electrical connections andinterconnections, and integrated circuitry comprising such contactopenings and electrical connections and interconnections.

BACKGROUND OF THE INVENTION

[0002] Referring to FIGS. 1 and 2, a semiconductor wafer fragment isindicated generally at 10 and comprises a semiconductive substrate 12.In the context of this document, the term “semiconductive substrate” isdefined to mean any construction comprising semiconductive material,including, but not limited to, bulk semiconductive materials such as asemiconductive wafer (either alone or in assemblies comprising othermaterials thereon), and semiconductive material layers (either alone orin assemblies comprising other materials). The term “substrate” refersto any supporting structure, including, but not limited to, thesemiconductive substrates described above. Substrate 12 comprises afield oxide region 13 having an outer surface 14 (FIG. 2) over which aplurality of conductive runners or conductive lines 16, 18, and 20 areformed. The illustrated conductive lines or runners include conductiveportions and insulative portions. Exemplary conductive portions areconstituted, in this example, by a respective polysilicon layer 22 andan overlying silicide layer 24. The insulative portions of the runnersor lines are constituted by respective overlying caps 26 and associatedsidewall spacers 28. Exemplary materials for the insulative portionsinclude oxides and nitrides.

[0003] An insulative layer 30 such as borophosphosilicate glass isformed over runners 16, 18, and 20 and a contact opening 32 is formedthrough a masked etch of layer 30 to outwardly expose a portion ofsilicide layer 24. Thereafter, conductive material such as conductivelydoped polysilicon is formed within contact opening 32 to provide aconductive contact 34 to conductive line 18. A metal layer 36 isprovided thereover to form an electrical connection with conductive line18.

[0004] A typical practice within the semiconductor industry is toprovide a conductive line or runner with a widened landing pad in orderto accommodate mask misalignments when contact openings are formed. Anexemplary widened landing pad is shown in FIGS. 1 and 2 at 38. By havinga widened landing pad, contact opening 32 can shift left or right somedistance relative to the position shown in Figs. 1 and 2 without makingundesirable contact with the substrate. For purposes of the ongoingdiscussion, landing pad 38 includes the conductive and insulativeportions of conductive line 18; and the conductive portions ofconductive line 18 define a contact pad with which electricalcommunication is desired. Accordingly, in the illustrated example acontact pad is defined by polysilicon layer 22 and silicide layer 24 ofconductive line 18. The contact pad defines a target area A inside ofwhich it is desirable to form a contact opening. An electricalconnection through contact opening 32 can be formed anywhere withintarget area A and still effectively make a desirable connection with theconductive contact pad. Hence, the target area tolerates a contactopening mask misalignment on either side of the illustrated and desiredcontact opening 32. A tradeoff for improved mask misalignment toleranceis a reduction in wafer real estate available for supporting conductivelines and other integrated circuitry components. This is due largely inpart to the increased area which is occupied by the widened landing pad38. This also adversely impacts the conductive line spacing such thatdesired minimum spacing adjacent conductive lines is not achieved.Hence, integrated circuitry cannot be packed as densely upon a wafer asis desirable when the widened landing pads are used.

[0005] This invention grew out of concerns associated with enhancing theefficiency with which wafer real estate is used to support integratedcircuitry. This invention also grew out of concerns associated withimproving the methods and structures through which contact is maderelative to conductive lines.

SUMMARY OF THE INVENTION

[0006] Methods of forming contact openings, making electricalinterconnections, and related integrated circuitry are described.Integrated circuitry formed through one or more of the inventivemethodologies is also described. In one implementation, a conductiverunner or line having a contact pad with which electrical communicationis desired is formed over a substrate outer surface. A conductive plugis formed laterally proximate the contact pad and together therewithdefines an effectively widened contact pad. Conductive material isformed within a contact opening which is received within insulativematerial over the effectively widened contact pad. In a preferredimplementation, a pair of conductive plugs are formed on either side ofthe contact pad laterally proximate thereof. The conductive plug(s) canextend away from the substrate outer surface a distance which is greateror less than a conductive line height of a conductive line adjacentwhich the plug is formed. In the former instance and in accordance withone aspect, such plug(s) can include a portion which overlaps with thecontact pad of the associated conductive line.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0008]FIG. 1 is a top plan view of a prior art semiconductor waferfragment and a plurality of conductive lines supported thereon.

[0009]FIG. 2 is a view which is taken along line 2-2 in FIG. 1 at asubsequent processing step.

[0010]FIG. 3 is a diagrammatic sectional view of a semiconductor waferfragment at one processing step in accordance with one implementation ofthe invention.

[0011]FIG. 4 is a view of the FIG. 3 wafer fragment at anotherprocessing step.

[0012]FIG. 5 is a view of the FIG. 3 wafer fragment at anotherprocessing step.

[0013]FIG. 6 is a view of the FIG. 3 wafer fragment at anotherprocessing step.

[0014]FIG. 7 is a view which is similar to the FIG. 6 view, but whichshows an alternate embodiment in accordance with another implementationof the invention.

[0015]FIG. 8 is a view of the FIG. 3 wafer fragment at anotherprocessing step.

[0016]FIGS. 9 and 10 are top plan views of semiconductor wafer fragmentswhich have been processed in accordance with the inventivemethodologies.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0018] Referring to FIG. 3, like numerals from the above-describedembodiment are utilized where appropriate, with differences beingindicated by the suffix “a” or with different numerals. Accordingly, aplurality of conductive runners or lines 16 a, 18 a, and 20 a are formedover outer surface 14, and can be formed over oxide isolation regions40. Exemplary isolation regions include shallow trench isolation regionsor field oxide regions formed through LOCOS techniques. The conductivelines comprise respective outermost surfaces 44 portions of which definerespective conductive line heights h outwardly of outer s surface 14.Diffusion regions 42 can be provided between the conductive lines, andpreferably comprise n-regions having doping concentrations of 1×10¹⁸cm⁻³. The diffusion regions can be provided in a separate doping step,or through outdiffusion of dopant from conductive material which willbecome more apparent below. An outer contact opening target area B isdefined by conductive line 18 a.

[0019] Referring to FIG. 4, an insulating material layer 46 is formedover substrate 12. An exemplary material is borophosphosilicate glass.

[0020] Referring to FIG. 5, at least one, and preferably a pair ofcontact openings 48, 50 are formed through layer 46 and preferablyoutwardly expose respective portions of outer surface 14. The contactopenings can be formed through a suitable masked etch of layer 46.Preferably, the individual contact openings are essentially self-alignedat and to the substrate at two locations 48 a, 48 b, and 50 a, 50 brespectively, along a line extending laterally from conductive runner orline 18 a. In a preferred implementation, one of the two locations forthe individual contact openings is defined by conductive runner 18 a.Even more preferably, the other of the two respective locations aredefined by respective next adjacent conductive lines 16 a, 20 a.

[0021] Referring to FIG. 6, and in accordance with a firstimplementation, first conductive material 52, 54 is formed withincontact openings 48, 50, between the illustrated conductive lines andlaterally proximate or adjacent the contact pad defined by conductiveline 18 a. An exemplary and preferred first conductive material isconductively doped polysilicon, which can serve as a source ofoutdiffused dopant for regions 42. The polysilicon can be chemical vapordeposited over the substrate and subsequently removed throughconventional processing to provide conductive plugs 56, 58. Suchconventional processing can include planarization processing to isolateconductive material within the respective contact openings, followed bya suitable timed etch to recess the conductive material within thecontact openings. In the illustrated example, conductive plugs areformed on both sides of conductive line 18 a. It is possible, however,for only one conductive plug to be formed on either side of conductiveline 18 a. The individual conductive plugs are essentially self-alignedat and to the substrate at the same locations as are the contactopenings in which each is formed.

[0022] Referring still to FIG. 6, the illustrated conductive plugs areformed to preferably extend outwardly from outer surface 14 a distancewhich is greater than conductive runner height h. Because the plugs inthis example are formed atop the same surface (outer surface 14) atopwhich the conductive lines are formed, each extends elevationally beyondthe respective conductive line heights. Such plugs could, however, beformed to extend from outer surface 14 a distance which is less than orno further than the conductive runner height. This could, for example,be done by conducting a timed etch for a longer period of time than issuitable for forming the illustrated FIG. 6 plugs. An exemplaryconstruction is shown in FIG. 7.

[0023] In one implementation, individual conductive plugs includeportions which overlap with portions of conductive line 18 a and therespective next adjacent conductive lines 16 a, 20 a. In a preferredimplementation, the respective plugs overlap with the outermost surfacesof the conductive lines adjacent which each is formed. Accordingly,portions of at least one, and preferably both conductive plugs canoverlap target area B. Collectively, the conductive material ofconductive plugs 56, 58, and the conductive material of conductive line18a define an effective contact pad having an outermost surface 60,which defines an effectively widened target area A′. The widened targetarea reduces the wafer area which was formerly required by the prior artwidened landing pad (FIGS. 1 and 2) described above.

[0024] Alternately considered, effective contact pad outermost surface60 defines a generally non-planar surface. In a preferredimplementation, at least one of the conductive plugs, and preferablyboth, define a region of outermost surface 60 having a highertopographical elevation than the region defined by the contact pad ofline 18 a.

[0025] Referring to FIG. 8, a layer 62 of insulative material is formedover the substrate and the effective contact pad. A contact opening 64is etched or otherwise formed through layer 62 to outwardly exposeportions of the effective contact pad. Preferably, the contact pad ofline 18 a is exposed, with any mask misalignment resulting in exposureof conductive material of either or both of conductive plugs 56, 58.Subsequently, a second conductive material 66 is formed within contactopening 64 and in electrical communication with at least portions of thecontact pad and, if exposed, an associated portion of a conductive plug.A bit line 68 can then be formed over the substrate and in electricalcommunication with material 66.

[0026] Referring to FIG. 9, conductive lines 16 a, 18 a and 20 a havefirst respective line widths w₁ at respective first locations and secondline widths w₂ at respective second locations, an exemplary second linewidth and location being shown for line 18 a. The second line widthcorresponds to a line location where at least a portion of contactopening 64 is formed. In one implementation, the first and second linewidths are essentially the same or equivalent. This is made possiblebecause the above-described conductive plugs 56, 58 (shown in dashedlines in FIGS. 9 and 10) reduce, if not eliminate, the requirement ofthe FIG. 1 widened landing pad. The illustrated conductive plugs providean effective contact pad width which is greater than second line widthw₂, and include respective portions proximate the first line width w₁which overlap with or extend elevationally over the conductive portions,e.g. the contact pad, of line 18 a. The plugs can also include portionswhich overlap with corresponding portions of conductive lines 16 a, 20a. This compensates for a contact opening mask misalignment by enablingdesired contact to be made through a respective one of the conductiveplugs as discussed above.

[0027] Referring to FIG. 10 and in accordance with anotherimplementation, localized first and second line widths w₁, w₂respectively, are different with second line width w₂ being greater thanfirst line width w₁. In this example, the second line width defines aportion of a landing pad which is smaller in dimension than the FIG. 1landing pad. Portions of conductive lines 16 b and 20 b laterallyproximate respective conductive plugs 56, 58 can be tapered or otherwiseconfigured to accommodate the somewhat wider landing pad.

[0028] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A semiconductor processing method of forming an electrical connectioncomprising: forming a conductive runner over a substrate outer surface,the conductive runner having a contact pad with which electricalcommunication is desired; forming a conductive plug laterally proximatethe contact pad; forming an insulative material over the contact pad andthe conductive plug; outwardly exposing at least some of the contact padand at least some of the conductive plug through the insulativematerial; and forming an electrical connection with and between thecontact pad and the conductive plug.
 2. The semiconductor processingmethod of claim 1, wherein: the conductive runner comprises an outermostsurface which defines a conductive runner height outwardly of thesubstrate outer surface; and the forming of the conductive plugcomprises forming the plug to extend outwardly from the substrate outersurface a distance which is less than the conductive runner height. 3.The semiconductor processing method of claim 1, wherein: the conductiverunner comprises an outermost surface which defines a conductive runnerheight outwardly of the substrate outer surface; and the forming of theconductive plug comprises forming the plug to extend outwardly from thesubstrate outer surface a distance which is greater than the conductiverunner height.
 4. The semiconductor processing method of claim 3,wherein the conductive plug comprises a portion which overlaps with theconductive runner's outermost surface.
 5. The semiconductor processingmethod of claim 1, wherein the forming of the conductive plug comprisesforming another conductive plug laterally proximate the contact pad, theconductive plugs being disposed on either side of the contact pad. 6.The semiconductor processing method of claim 5, wherein: the conductiverunner comprises an outermost surface which defines a conductive runnerheight outwardly of the substrate outer surface; and the forming of theconductive plugs comprise forming the plugs to extend outwardly from thesubstrate outer surface respective distances which are greater than theconductive runner height.
 7. The semiconductor processing method ofclaim 6, wherein at least one of the conductive plugs comprises aportion which overlaps with the conductive runner's outermost surface.8. The semiconductor processing method of claim 6, wherein bothconductive plugs comprise respective portions which overlap with theconductive runner's outermost surface.
 9. A method of forming a contactopening to a conductive runner comprising: forming a conductive runnerhaving an outer contact opening target area over a semiconductivesubstrate; forming at least one conductive plug within insulatingmaterial laterally adjacent the runner target area, the plug beingformed within a contact opening in the insulating material which isessentially self aligned at and to the semiconductive substrate at twolocations along a line extending laterally from the conductive runner;and etching a contact opening to and overlapping the runner target areaand plug through insulative material overlying the runner and plug. 10.The method of forming a contact opening of claim 9, wherein: theconductive runner comprises an outermost surface which defines aconductive runner height outwardly of a substrate outer surface; and theforming of the conductive plug comprises forming the plug to extendoutwardly from the substrate outer surface a distance which is less thanthe conductive runner height.
 11. The method of forming a contactopening of claim 9, wherein one of the self-aligned locations is definedby the conductive runner.
 12. The method of forming a contact opening ofclaim 11, wherein the other of the self-aligned locations is defined bya next adjacent conductive runner.
 13. The method of forming a contactopening of claim 9, wherein: the conductive runner comprises anoutermost surface which defines a conductive runner height outwardly ofa substrate outer surface; and the forming of the conductive plugcomprises forming the plug to extend outwardly from the substrate outersurface a distance which is greater than the conductive runner height.14. The method of forming a contact opening of claim 13, wherein theconductive plug comprises a portion which overlaps with the target area.15. The method of forming a contact opening of claim 9, wherein: theforming of the conductive plug comprises forming another conductive plugwithin the insulating material laterally adjacent the runner targetarea, the conductive plugs being disposed on either side of the runnertarget area.
 16. The method of forming a contact opening of claim 15,wherein one of the respective self-aligned locations for individualconductive plugs is defined by the conductive runner, and the otherrespective self-aligned location is defined by respective next adjacentconductive runners.
 17. The method of forming a contact opening of claim16, wherein: the conductive runner comprises an outermost surface whichdefines a conductive runner height outwardly of a substrate outersurface; and the forming of the conductive plugs comprise forming bothplugs to extend outwardly from the substrate outer surface a distancewhich is greater than the conductive runner height and to overlap withthe target area.
 18. The method of forming a contact opening of claim16, wherein: the conductive runner comprises an outermost surface whichdefines a conductive runner height outwardly of a substrate outersurface; and the forming of the conductive plugs comprise forming bothplugs to extend outwardly from the substrate outer surface a distancewhich is less than the conductive runner height.
 19. A semiconductorprocessing method of forming a contact opening to a conductive linecomprising: forming a conductive line over a substrate outer surface,the conductive line having a first line width at one location and asecond line width which is different from the first line width atanother location; at least a portion of the second line width defining acontact pad with which electrical connection is desired; forming aconductive plug laterally proximate the contact pad, the conductive plugand the contact pad defining an effective contact pad having aneffective contact pad width which is greater than the second line width;and after forming the conductive plug, etching a contact opening to atleast a portion of the effective contact pad through insulative materialoverlying the conductive line and plug.
 20. The semiconductor processingmethod of claim 19, wherein the second line width is greater than thefirst line width.
 21. The semiconductor processing method of claim 19,wherein the effective contact pad comprises a generally non-planaroutermost surface.
 22. The semiconductor processing method of claim 21,wherein the conductive plug defines a region of the outermost surfacehaving a higher topographical elevation than a region of the outermostsurface defined by the contact pad.
 23. The semiconductor processingmethod of claim 21, wherein the forming of the conductive plug comprisesforming another conductive plug laterally proximate the contact pad, theconductive plugs being disposed on either side thereof and togethertherewith defining the effective contact pad.
 24. The semiconductorprocessing method of claim 23, wherein at least one of the conductiveplugs defines a region of the outermost surface having a highertopographical elevation than a region of the outermost surface definedby the contact pad.
 25. The semiconductor processing method of claim 24,wherein both of the conductive plugs define respective regions of theoutermost surface having higher respective topographical elevations thana region of the outermost surface defined by the contact pad.
 26. Asemiconductor processing method of forming an electrical interconnectioncomprising: forming a plurality of conductive lines over a substrateouter surface, individual conductive lines having contact pads withwhich electrical communication is desired; forming a conductive plug atleast a portion of which is disposed laterally adjacent and between acontact pad and a next adjacent conductive line; forming an insulativematerial over the contact pad and the conductive plug; forming anopening through the insulative material over the contact pad and theconductive plug; and forming conductive material within the opening. 27.The semiconductor processing method of claim 26, wherein: the conductiveline comprises an outermost surface which defines a conductive lineheight outwardly of the substrate outer surface; and the forming of theconductive plug comprises forming the plug to elevationally extend nofurther than the conductive line height.
 28. The semiconductorprocessing method of claim 26, wherein: the conductive line comprises anoutermost surface which defines a conductive line height outwardly ofthe substrate outer surface; and the forming of the conductive plugcomprises forming the plug to extend elevationally beyond the conductiveline height.
 29. The semiconductor processing method of claim 28,wherein the conductive plug comprises a portion which overlaps with theconductive line's outermost surface.
 30. The semiconductor processingmethod of claim 28, wherein the conductive plug comprises a portionwhich overlaps with a portion of the next adjacent conductive line. 31.The semiconductor processing method of claim 26, wherein: the forming ofthe conductive plug comprises forming another conductive plug at least aportion of which is disposed laterally adjacent and between the contactpad and another next adjacent conductive line, the conductive plugsbeing disposed on either side of the contact pad.
 32. The semiconductorprocessing method of claim 31, wherein: the conductive lines compriseoutermost surfaces which define conductive line heights; and the formingof the conductive plugs comprises forming the plugs to extendelevationally beyond the conductive line height, at least one of theplugs comprising a portion which overlaps with a conductive lineoutermost surface.
 33. A semiconductor processing method of forming aconductive interconnection comprising: forming a plurality of conductivelines over a substrate outer surface, individual conductive lines havingrespective first line widths at respective first locations andrespective second line widths at respective second locations which aredifferent from the respective first locations; at least portions of therespective second line widths being greater than the first line widthsand having conductive portions which define respective contact pads withwhich electrical communication is desired; at least one conductive linesecond line width being disposed laterally proximate at least oneconductive line first line width of an adjacent line; forming a firstconductive material between the at least one conductive line second linewidth and the at least one conductive line first line width; forminginsulative material over the substrate; etching an opening through theinsulative material and over at least one contact pad; and forming asecond conductive material within the opening.
 34. The semiconductorprocessing method of claim 33, wherein the forming of the firstconductive material comprises forming the conductive material to overlapwith the portion of the second line width defining the contact padlaterally proximate the one conductive line first line width.
 35. Thesemiconductor processing method of claim 33 further comprising prior toforming the first conductive material, forming an insulating materialover the substrate; and forming a contact opening through the insulatingmaterial which is essentially self-aligned relative to the oneconductive line second line width and its associated adjacent line firstline width.
 36. The semiconductor processing method of claim 33,wherein: the one conductive line second line width is disposed laterallyproximate and between a pair of conductive line first line widths ofdifferent adjacent lines; and the forming of the first conductivematerial comprises forming the conductive material between the oneconductive line second line width and the conductive line first linewidths of the pair.
 37. The semiconductor processing method of claim 36,wherein the forming of the first conductive material comprises forming apair of conductive plugs respective individual plugs of the pair beingdisposed between the one conductive line second line width andindividual respective conductive line first line widths, at least one ofthe plugs overlapping with the one conductive line second line width.38. A method of forming a contact opening to a conductive linecomprising: forming a conductive line over a semiconductive substrate,the conductive line having a conductive line width and a target areawith which electrical communication is desired; forming a pair ofconductive plugs laterally proximate the target area on either side ofthe conductive line and defining together therewith an effectivelywidened target area, the conductive plugs being self-aligned to thesubstrate adjacent the conductive line; forming a material at least overthe effectively widened target area; and outwardly exposing at least aportion of the widened target area through the material.
 39. The methodof forming a contact opening of claim 38, wherein the forming of thepair of conductive plugs comprises forming at least one of theconductive plugs between the conductive line and a next adjacentconductive line.
 40. The method of forming a contact opening of claim38, wherein the forming of the pair of conductive plugs comprisesforming the conductive plugs between the conductive line and respectivenext adjacent conductive lines.
 41. The method of forming a contactopening of claim 38, wherein the forming of the pair of conductive plugscomprises forming at least one of the plugs to overlap with the targetarea.
 42. The method of forming a contact opening of claim 38, whereinthe forming of the pair of conductive plugs comprises forming the plugsto overlap with the target area.
 43. Integrated circuitry comprising: asemiconductive substrate having an outer surface; a first and secondconductive runner disposed over the outer surface; a contact padcomprising part of the first conductive runner; and a conductive plugdisposed over the outer surface laterally proximate and between thecontact pad and the second conductive runner, the conductive plug beingessentially self-aligned at and to the semiconductive substrate at twolocations one of which being defined by the second conductive runner.44. The integrated circuitry of claim 43, wherein: the first conductiverunner comprises an outermost surface which defines a conductive runnerheight; and the conductive plug extends away from the substrate outersurface a distance which is greater than the first conductive runnerheight.
 45. The integrated circuitry of claim 44, wherein the conductiveplug comprises a portion which overlaps with the conductive runner'soutermost surface.
 46. The integrated circuitry of claim 44, furthercomprising: a third conductive runner disposed over the outer surfaceadjacent the first conductive runner; and a second conductive plugdisposed over the outer surface laterally proximate and between thecontact pad and the third conductive runner, the conductive plug beingessentially self-aligned at and to the semiconductive substrate at twolocations one of which being defined by the third conductive runner. 47.The integrated circuitry of claim 46, wherein the second conductive plugextends away from the substrate outer surface a distance which isgreater than the first conductive runner height.
 48. The integratedcircuitry of claim 47, wherein the second conductive plug comprises aportion which overlaps with the conductive runner's outermost surface.49. Integrated circuitry comprising: a semiconductive substrate havingan outer surface; a conductive line disposed over the outer surface andhaving a conductive portion which defines a contact pad with whichelectrical connection is desired; at least one conductive plug disposedlaterally proximate the contact pad and having a plug portion disposedelevationally over a portion of the contact pad; and conductive materialdisposed over the contact pad and in electrical communication with atleast a portion of the conductive plug.
 50. Integrated circuitrycomprising: a semiconductive substrate having an outer surface; aconductive line disposed over the outer surface and having a first linewidth at one location and a second line width which is different fromthe first line width at another location; at least a portion of thesecond line width defining a contact pad with which electricalconnection is desired; a conductive plug disposed laterally proximatethe contact pad and defining therewith an effective contact pad havingan effective contact pad width which is greater than the second linewidth; and conductive material disposed over the effective contact padand making electrical connection with at least a portion of theconductive plug.
 51. Integrated circuitry comprising: a semiconductivesubstrate having an outer surface; a conductive line disposed over theouter surface and having a conductive line width and a target area withwhich electrical communication is desired; a pair of conductive plugsdisposed over the outer surface on either side of the conductive linelaterally proximate the target area and self-aligned to the substrateadjacent the conductive line, the plugs and target area defining aneffectively widened target area; and conductive material disposed overand in electrical communication with at least a portion of theeffectively widened target area which includes the conductive linetarget area.